Peregrine Semiconductor Corporation announced today the release of its Rad-Hard 0.5 micron cell library for customer ASIC designs using its patented Ultra Thin Silicon (UTSi) process.
With the capability to integrate over 750,000 gates of CMOS Silicon-On-Sapphire (SOS) random logic (above 1 million equivalent gates with embedded macros), this cell library offers customers the unprecedented high-speed and low power consumption of UTSi technology for a broad range of space applications.
"There is an urgent need for an advanced rad-hard process technology that system designers can rely on to develop next generations of advanced signal processing and other system control functions," said Chuck Tabbert, Peregrine's Director of Space & Defense Marketing.
"Our focused development activity in UTSi, including Radio Frequency (RF) synthesizer and transceiver blocks, A/D converters, embedded EEPROM, SRAM or ROM will continue to enhance the capability of the cell library in the near future."
The UTSi process is presently being processed at Peregrine's fab partner in Japan, according to Tabbert, and will soon be installed in Peregrine's newly acquired 6 inch fabrication facility in Sydney, Australia.
Production from this new fab will be available this summer. Tabbert further added that the UTSi process technology is planned to be scaled down to 0.25 micron, which the company expects to be available for customer designs by Q3/2001.
